Graphics Processing Unit (GPU) now possesses the capability to render images of giga-byte magnitude. As the trend of computer graphics moves towards higher-resolution display, such as, 4K×4K, and complex rendering, the capability of computation and bandwidth of interface between GPU and system is critical. However, for handheld devices, possessing powerful computation capability and large bandwidth is not realistic because of huge power consumption. The tile-based rendering technique, wherein a frame is divided into a plurality of tiles for rendering, is proposed to help GPU in better exploring the locality of memory access, utilizing efficient use of traffic bandwidth and better scheduling of shader computation to achieve better performance.
FIG. 1 shows a schematic view of the structure of an apparatus realizing the GPU rendering pipeline in known technique. As shown in FIG. 1, the apparatus includes an application programming interface (API) 101, a state and vertex shader 102, a primitive operation unit 103, a rasterizer 104, a fragment shader 105, a depth stencil 106, a color buffer blender 107, a dither unit 108 and a frame buffer 109.
Other techniques, such as, scheduling graphic commands based on property and function, dispatching the commands to respective hardware and collecting the result in display driver, and by using a sampling mechanism and utilizing previously rendered and sampled pixels to reconstruct a new frame are also proposed.